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PRELIMINARY
CY14B101LA, CY14B101NA
1 Mbit (128K x 8/64K x 16) nvSRAM
Features

Functional Description
The Cypress CY14B101LA/CY14B101NA is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as 128K bytes of 8 bits each or 64K words of 16 bits each. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world's most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control.
20 ns, 25 ns, and 45 ns Access Times Internally Organized as 128K x 8 (CY14B101LA) or 64K x 16 (CY14B101NA) Hands off Automatic STORE on Power Down with only a Small Capacitor STORE to QuantumTrap Nonvolatile Elements Initiated by Software, Device Pin, or AutoStore on Power Down RECALL to SRAM Initiated by Software or Power Up Infinite Read, Write, and Recall Cycles 200,000 STORE Cycles to QuantumTrap 20 year Data Retention Single 3V +20% to -10% Operation Commercial and Industrial Temperatures 54/44-Pin TSOP-II, 48-Pin SSOP, and 32-Pin SOIC Packages Pb-free and RoHS Compliance
Logic Block Diagram[1, 2, 3]
Notes 1. Address A0 - A16 for x8 configuration and Address A0 - A15 for x16 configuration. 2. Data DQ0 - DQ7 for x8 configuration and Data DQ0 - DQ15 for x16 configuration. 3. BHE and BLE are applicable for x16 configuration only.
Cypress Semiconductor Corporation Document #: 001-42879 Rev. *C
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised July 09, 2009
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PRELIMINARY
CY14B101LA, CY14B101NA
Pinouts
Figure 1. Pin Diagram - 44 Pin TSOP II
NC [7] NC A0 A1 A2 A3 A4 CE DQ0 DQ1 VCC VSS DQ2 DQ3 WE A5 A6 A7 A8 A9 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 HSB NC [6] NC NC NC [5] A16 [4] A15 OE DQ7 DQ6 VSS VCC DQ5 DQ4 VCAP A14 A13 A12 A11 A10 NC NC A0 A1 A2 A3 A4 CE DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC [5] A15 OE[4] BHE BLE DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 VCAP A14 A13 A12 A11 A10
44 - TSOP II
(x8)
44 - TSOP II
(x16)
[8]
Top View (not to scale)
Top View (not to scale)
Figure 2. Pin Diagram - 48-Pin SSOP and 32-Pin SOIC
VCAP A16 A14 A12 A7 A6 A5 NC A4 NC NC NC VSS NC NC DQ0 A3 A2 A1 A0 DQ1 DQ2 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC A15 HSB WE A13 A8 A9 NC A11 NC NC NC VSS NC NC DQ6 OE A10 CE DQ7 DQ5 DQ4 DQ3 VCC
48-SSOP
Top View (not to scale)
Notes 4. Address expansion for 2 Mbit. NC pin not connected to die. 5. Address expansion for 4 Mbit. NC pin not connected to die. 6. Address expansion for 8 Mbit. NC pin not connected to die. 7. Address expansion for 16 Mbit. NC pin not connected to die. 8. HSB pin is not available in 44-TSOP II (x16) package.
Document #: 001-42879 Rev. *C
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PRELIMINARY
CY14B101LA, CY14B101NA
Pinouts
(continued) Figure 3. Pin Diagram - 54-Pin TSOP II
NC [7] NC A0 A1 A2 A3 A4 CE DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A5 A6 A7 A8 A9 NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 HSB NC [6] [5] NC [4] NC A15 OE BHE BLE DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 VCAP A14 A13 A12 A11 A10 NC NC NC
54 - TSOP II
(x16)
Top View (not to scale)
Table 1. Pin Definitions Pin Name A0 - A16 A0 - A15 I/O Type Input Description Address Inputs Used to Select one of the 131,072 Bytes of the nvSRAM for x8 Configuration. Address Inputs Used to Select one of the 65,536 Words of the nvSRAM for x16 Configuration.
Bidirectional Data I/O Lines for x8 Configuration. Used as input or output lines depending on operation. DQ0 - DQ7 DQ0 - DQ15 Input/Output Bidirectional Data I/O Lines for x16 Configuration. Used as input or output lines depending on operation. WE CE OE BHE BLE VSS VCC HSB[8] Input Input Input Input Input Ground Power Supply Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written to the specific address location. Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. I/O pins are tristated on deasserting OE HIGH. Byte High Enable, Active LOW. Controls DQ15 - DQ8. Byte Low Enable, Active LOW. Controls DQ7 - DQ0. Ground for the Device. Must be connected to the ground of the system. Power Supply Inputs to the Device. 3.0V +20%, -10%
Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress. When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin HIGH if not connected (connection optional). After each STORE operation HSB is driven HIGH for short time with standard output high current. Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to nonvolatile elements.
VCAP NC
No Connect No Connect. This pin is not connected to the die.
Document #: 001-42879 Rev. *C
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PRELIMINARY
CY14B101LA, CY14B101NA
Device Operation
The CY14B101LA/CY14B101NA nvSRAM is made up of two functional components paired in the same physical cell. They are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture, all cells are stored and recalled in parallel. During the STORE and RECALL operations, SRAM read and write operations are inhibited. The CY14B101LA/CY14B101NA supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 200K STORE operations. Refer to the Truth Table For SRAM Operations on page 16 for a complete description of read and write modes.
Note If the capacitor is not connected to VCAP pin, AutoStore must be disabled using the soft sequence specified in Preventing AutoStore on page 6. In case AutoStore is enabled without a capacitor on VCAP pin, the device attempts an AutoStore operation without sufficient charge to complete the Store. This may corrupt the data stored in nvSRAM. Figure 4 shows the proper connection of the storage capacitor (VCAP) for automatic STORE operation. Refer to DC Electrical Characteristics on page 8 for the size of VCAP. The voltage on the VCAP pin is driven to VCC by a regulator on the chip. Place a pull up on WE to hold it inactive during power up. This pull up is only effective if the WE signal is tristate during power up. Many MPUs tristate their controls on power up. This must be verified when using the pull up. When the nvSRAM comes out of power-on-recall, the MPU must be active or the WE held inactive until the MPU comes out of reset. To reduce unnecessary nonvolatile stores, AutoStore and Hardware STORE operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a write operation has taken place. The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress. Figure 4. AutoStore Mode
Vcc
SRAM Read
The CY14B101LA/CY14B101NA performs a read cycle when CE and OE are LOW and WE and HSB are HIGH. The address specified on pins A0-16 or A0-15 determines which of the 131,072 data bytes or 65,536 words of 16 bits each are accessed. Byte enables (BHE, BLE) determine which bytes are enabled to the output, in the case of 16-bit words. When the read is initiated by an address transition, the outputs are valid after a delay of tAA (read cycle 1). If the read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (read cycle 2). The data output repeatedly responds to address changes within the tAA access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW.
0.1uF 10kOhm Vcc
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB is HIGH. The address inputs must be stable before entering the write cycle and must remain stable until CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins DQ0-15 are written into the memory if the data is valid tSD before the end of a WE-controlled write or before the end of a CE-controlled write. The Byte Enable inputs (BHE, BLE) determine which bytes are written, in the case of 16-bit words. Keep OE HIGH during the entire write cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW.
WE
VCAP
VSS
VCAP
Hardware STORE Operation
The CY14B101LA/CY14B101NA provides the HSB[8] pin to control and acknowledge the STORE operations. Use the HSB pin to request a Hardware STORE cycle. When the HSB pin is driven LOW, the CY14B101LA/CY14B101NA conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a write to the SRAM has taken place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress. SRAM write operations that are in progress when HSB is driven LOW by any means are given time (tDELAY) to complete before the STORE operation is initiated. However, any SRAM write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. In case the write latch is not set, HSB is not driven LOW by the CY14B101LA/CY14B101NA. But any SRAM read and write cycles are inhibited until HSB is returned HIGH by MPU or other external source. Page 4 of 24
AutoStore Operation
The CY14B101LA/CY14B101NA stores data to the nvSRAM using one of the following three storage operations: Hardware STORE activated by HSB; Software STORE activated by an address sequence; AutoStore on device power down. The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B101LA/CY14B101NA. During a normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor.
Document #: 001-42879 Rev. *C
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PRELIMINARY
CY14B101LA, CY14B101NA
During any STORE operation, regardless of how it is initiated, the CY14B101LA/CY14B101NA continues to drive the HSB pin LOW, releasing it only when the STORE is complete. Upon completion of the STORE operation, the CY14B101LA/CY14B101NA remains disabled until the HSB pin returns HIGH. Leave the HSB unconnected if it is not used.
The software sequence may be clocked with CE controlled reads or OE controlled reads, with WE kept HIGH for all the six READ sequences. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. HSB is driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the read and write operation.
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC< VSWITCH), an internal RECALL request is latched. When VCC again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. During this time, HSB is driven low by the HSB driver.
Software RECALL
Data is transferred from nonvolatile memory to the SRAM by a software address sequence. A Software RECALL cycle is initiated with a sequence of read operations in a manner similar to the Software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled read operations must be performed: 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x4C63 Initiate RECALL Cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared. Next, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for read and write operations. The RECALL operation does not alter the data in the nonvolatile elements.
Software STORE
Data is transferred from SRAM to the nonvolatile memory by a software address sequence. The CY14B101LA/CY14B101NA Software STORE cycle is initiated by executing sequential CE controlled read cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence is aborted and no STORE or RECALL takes place. To initiate the Software STORE cycle, the following read sequence must be performed: 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x8FC0 Initiate STORE Cycle Table 2. Mode Selection CE H L L L WE X H L H OE, BHE, BLE[3] X L X L
A15 - A0[9] X X X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45
Mode Not Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable
I/O Output High Z Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output Data
Power Standby Active Active Active[10]
Notes 9. While there are 17 address lines on the CY14B101LA (16 address lines on the CY14B101NA), only the 13 address lines (A14 - A2) are used to control software modes. Rest of the address lines are don't care. 10. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
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PRELIMINARY
CY14B101LA, CY14B101NA
Table 2. Mode Selection (continued) CE L WE H OE, BHE, BLE[3] L A15 - A0[9] 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Mode Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall I/O Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z Power Active[10]
L
H
L
Active ICC2[10]
L
H
L
Active[10]
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the Software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8B45 AutoStore Disable The AutoStore is reenabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a manner similar to the Software RECALL initiation. To initiate the AutoStore enable sequence, the following sequence of CE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or reenabled, a manual STORE operation (Hardware or Software) must be issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled.
Data Protection
The CY14B101LA/CY14B101NA protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC is less than VSWITCH. If the CY14B101LA/CY14B101NA is in a write mode (both CE and WE are LOW) at power up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after tLZHSB (HSB to output active). This protects against inadvertent writes during power up or brown out conditions.
Noise Considerations
Refer to CY application note AN1064.
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PRELIMINARY
CY14B101LA, CY14B101NA
Best Practices
nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product's main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices:
Power up boot firmware routines should rewrite the nvSRAM into the desired state (for example, autostore enabled). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently such as program bugs and incoming inspection routines. The VCAP value specified in this data sheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the maximum VCAP value because the nvSRAM internal algorithm calculates VCAP charge and discharge time based on this max VCAP value. Customers that want to use a larger VCAP value to make sure there is extra store charge and store time should discuss their VCAP size selection with Cypress to understand any impact on the VCAP voltage level at the end of a tRECALL period.
The nonvolatile cells in this nvSRAM product are delivered from Cypress with 0x00 written in all cells. Incoming inspection routines at customer or contract manufacturer's sites sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product's firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on should always program a unique NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently.
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PRELIMINARY
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................... -65C to +150C Maximum Accumulated Storage Time: At 150C Ambient Temperature........................ 1000h At 85C Ambient Temperature..................... 20 Years Ambient Temperature with Power Applied ..-55C to +150C Supply Voltage on VCC Relative to GND.......... -0.5V to 4.1V Voltage Applied to Outputs in High-Z State -0.5V to VCC + 0.5V Input Voltage ............................................ -0.5V to Vcc+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential.................. -2.0V to VCC + 2.0V
CY14B101LA, CY14B101NA
Package Power Dissipation Capability (TA = 25C) ....................................................1.0W Surface Mount Pb Soldering Temperature (3 Seconds)...........................................+260C DC Output Current (1 output at a time, 1s duration)......15 mA Static Discharge Voltage ......................................... > 2001V (per MIL-STD-883, Method 3015) Latch Up Current................................................... > 200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 2.7V to 3.6V
DC Electrical Characteristics
Over the Operating Range (VCC = 2.7V to 3.6V) Parameter VCC ICC1 Description Power Supply Voltage Average VCC Current tRC = 20 ns tRC = 25 ns tRC = 45 ns Values obtained without output loads (IOUT = 0 mA) All Inputs Don't Care, VCC = Max Average current for duration tSTORE 35 Commercial Test Conditions Min 2.7 Typ[11] 3.0 Max 3.6 65 65 50 70 70 52 10 Unit V mA mA mA mA mA mA mA mA
Industrial
ICC2 ICC3
Average VCC Current during STORE
Average VCC Current at All I/P cycling at CMOS levels. tRC= 200 ns, Values obtained without output loads (IOUT = 0 mA) VCC (Typ), 25C Average VCAP Current All Inputs Don't Care, VCC = Max during AutoStore Cycle Average current for duration tSTORE VCC Standby Current CE > (VCC - 0.2V). VIN < 0.2V or > (VCC - 0.2V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz -1 -100 -1 2.0 Vss-0.5 IOUT = -2 mA IOUT = 4 mA Between VCAP pin and VSS, 5V Rated 61 2.4
ICC4 ISB IIX[12]
5 5
mA mA
Input Leakage Current VCC = Max, VSS < VIN < VCC (except HSB) Input Leakage Current VCC = Max, VSS < VIN < VCC (for HSB)
+1 +1 +1 VCC+0.5 0.8 0.4 68 180
A A A V V V V F
IOZ VIH VIL VOH VOL VCAP
Off-State Output Leakage Current Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Storage Capacitor
VCC = Max, VSS < VOUT < VCC, CE or OE > VIH or BHE/BLE > VIH or WE < VIL
Notes 11. Typical values are at 25C, VCC= VCC (Typ). Not 100% tested. 12. The HSB pin has IOUT = -2 uA for VOH of 2.4V when both active high and low drivers are disabled. When they are enabled standard VOH and VOL are valid. This parameter is characterized but not tested.
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PRELIMINARY
CY14B101LA, CY14B101NA
Data Retention and Endurance
Parameter DATAR NVC Data Retention Nonvolatile STORE Operations Description Min 20 200 Unit Years K
Capacitance
Parameter[13] CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC (Typ) Max 7 7 Unit pF pF
Thermal Resistance
Parameter[13] Description Test Conditions 54-TSOP II 48-SSOP 44-TSOP II 30.73 6.08 TBD TBD 31.11 5.56 32-SOIC TBD TBD Unit C/W C/W
JA JC
Thermal Resistance Test conditions follow standard (Junction to Ambient) test methods and procedures for Thermal Resistance measuring thermal impedance, in accordance with EIA/JESD51. (Junction to Case)
Figure 5. AC Test Loads
577 3.0V OUTPUT 30 pF R2 789 R1
577 3.0V OUTPUT 5 pF R1
for tristate specs
R2 789
AC Test Conditions
Input Pulse Levels ....................................................0V to 3V Input Rise and Fall Times (10% - 90%) ........................ <3 ns Input and Output Timing Reference Levels .................... 1.5V
Note 13. These parameters are guaranteed by design and are not tested.
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PRELIMINARY
CY14B101LA, CY14B101NA
AC Switching Characteristics
Parameters Description Cypress Alt Parameters Parameters SRAM Read Cycle tACS Chip Enable Access Time tACE [14] tRC Read Cycle Time tRC tAA[15] tDOE tOHA
[15]
20 ns Min Max 20 20 20 10 3 3 8 0 8 0 20 10 0 8 20 15 15 8 0 15 0 0 8 3 15 3 20 25 20 20 10 0 20 0 0 0 0 0 3 3 25
25 ns Min Max 25 45 25 12 3 3 10 0 10 0 25 12 0 10 45 30 30 15 0 30 0 0 10 3 30
45 ns Min Max 45 45 20 Unit
ns ns ns ns ns ns
tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA
Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby Byte Enable to Data Valid Byte Enable to Output Active Byte Disable to Output Inactive Write Cycle Time Write Pulse Width Chip Enable To End of Write Data Setup to End of Write Data Hold After End of Write Address Setup to End of Write Address Setup to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active after End of Write Byte Enable to End of Write
tLZCE[13, 16] tHZCE
[13, 16]
15 15 45 20 15
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tLZOE[13, 16] tHZOE
[13, 16]
tPU[13]
[13]
tPS tPD tDBE[[13] tLZBE[13] tHZBE[13] SRAM Write Cycle tWC tWC tWP tPWE tCW tSCE tDW tSD tDH tHD tAW tAW tAS tSA tWR tHA [13, 16,17] tWZ tHZWE tLZWE tBW
[13, 16]
15
tOW -
Switching Waveforms
Figure 6. SRAM Read Cycle #1: Address Controlled [14, 15, 18]
tRC Address Address Valid tAA Data Output Previous Data Valid tOHA Output Data Valid
Notes 14. WE must be HIGH during SRAM read cycles. 15. Device is continuously selected with CE, OE and BHE/BLE LOW. 16. Measured 200 mV from steady state output voltage. 17. If WE is low when CE goes low, the outputs remain in the high impedance state. 18. HSB must remain HIGH during Read and Write cycles.
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PRELIMINARY
CY14B101LA, CY14B101NA
Figure 7. SRAM Read Cycle #2: CE and OE Controlled [3, 14, 18]
Address Address Valid tRC tACE CE tAA tLZCE OE tLZOE tDBE BHE, BLE tLZBE Data Output High Impedance tPU Standby Active Output Data Valid tPD tDOE tHZBE tHZOE tHZCE
ICC
Figure 8. SRAM Write Cycle #1: WE Controlled [3, 17, 18, 21]
tWC Address Address Valid tSCE CE tBW BHE, BLE tAW tPWE WE tSA tSD Data Input tHZWE Data Output Previous Data tHD Input Data Valid tLZWE High Impedance tHA
Note 21. CE or WE must be > VIH during address transitions.
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PRELIMINARY
CY14B101LA, CY14B101NA
Figure 9. SRAM Write Cycle #2: CE Controlled [3, 17, 18, 21]
tWC Address tSA CE tBW BHE, BLE tPWE WE tSD Data Input Data Output Input Data Valid High Impedance tHD Address Valid tSCE tHA
Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled [3, 17, 18, 21]
tWC Address tSCE CE tSA BHE, BLE tAW tPWE WE tSD Data Input tHD Input Data Valid High Impedance Data Output tBW tHA Address Valid
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PRELIMINARY
CY14B101LA, CY14B101NA
AutoStore/Power Up RECALL
Parameters Description 20 ns Min Max 20 8 20 2.65 150 1.9 5 500 150 1.9 5 500 Min 25 ns Max 20 8 25 2.65 150 1.9 5 500 Min 45 ns Max 20 8 25 2.65 Unit ms ms ns V s V s ns
tHRECALL [27] Power Up RECALL Duration tSTORE [23] STORE Cycle Duration tDELAY [24] VSWITCH tVCCRISE
[13]
Time Allowed to Complete SRAM Write Cycle Low Voltage Trigger Level VCC Rise Time HSB Output Disable Voltage HSB To Output Active Time HSB High Active Time
VHDIS tLZHSB[13] tHHHD[13]
[13]
Switching Waveforms
Figure 11. AutoStore or Power Up RECALL[27]
VCC VSWITCH VHDIS
23
VVCCRISE tHHHD HSB OUT
Note
23
tSTORE tHHHD
Note
tSTORE Note
26
tDELAY tLZHSB tDELAY tLZHSB
AutoStore
POWERUP RECALL Read & Write Inhibited (RWI)
tHRECALL
tHRECALL
POWER-UP RECALL
Read & Write
BROWN OUT AutoStore
POWER-UP RECALL
Read & Write
POWER DOWN AutoStore
Notes 22. tHRECALL starts from the time VCC rises above VSWITCH. 23. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place. 24. On a Hardware Store and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY. 25. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH. 26. HSB pin is driven high to VCC only by internal 100 k resistor, HSB driver is disabled.
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PRELIMINARY
CY14B101LA, CY14B101NA
Software Controlled STORE/RECALL Cycle
Parameters[27, 28] tRC tSA tCW tHA tRECALL Description STORE/RECALL Initiation Cycle Time Address Setup Time Clock Pulse Width Address Hold Time RECALL Duration Min 20 0 15 0 200 20 ns Max Min 25 0 20 0 200 25 ns Max Min 45 0 30 0 200 45 ns Max Unit ns ns ns ns s
Switching Waveforms
Figure 12. CE and OE Controlled Software STORE/RECALL Cycle[28]
tRC Address tSA CE tSA OE tHHHD HSB (STORE only) DQ (DATA) tLZCE tHZCE t DELAY Note
29
tRC Address #6 tCW tHA tHA
Address #1 tCW
tHA tHA
tLZHSB High Impedance tSTORE/tRECALL
RWI
Figure 13. Autostore Enable/Disable Cycle
tRC Address tSA CE tSA Address #1 tCW tHA tHA tRC Address #6 tCW
tHA tHA
OE tLZCE DQ (DATA) tHZCE tSS Note
29
t DELAY
Notes 27. The software sequence is clocked with CE controlled or OE controlled reads. 28. The six consecutive addresses must be read in the order listed in Table 2 on page 5. WE must be HIGH during all six consecutive cycles. 29. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time.
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PRELIMINARY
CY14B101LA, CY14B101NA
Hardware STORE Cycle
Parameters tDHSB tPHSB tSS [29, 30] Description HSB To Output Active Time when write latch not set Hardware STORE Pulse Width Soft Sequence Processing Time 15 100 20 ns Min Max 20 15 100 Min 25 ns Max 25 15 100 Min 45 ns Max 25 Unit ns ns s
Switching Waveforms
Figure 14. Hardware STORE Cycle[23]
Write latch set
tPHSB HSB (IN) tSTORE tDELAY HSB (OUT) tLZHSB DQ (Data Out) RWI tHHHD
Write latch not set
tPHSB HSB (IN) HSB pin is driven high to VCC only by Internal 100kOhm resistor, HSB driver is disabled SRAM is disabled as long as HSB (IN) is driven low. tDELAY tDHSB tDHSB
HSB (OUT) RWI
Figure 15. Soft Sequence Processing[29, 30]
Soft Sequence Command Address Address #1 tSA Address #6 tCW tSS Soft Sequence Command Address #1 Address #6 tCW tSS
CE VCC
Notes 29. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command. 30. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
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PRELIMINARY
CY14B101LA, CY14B101NA
Truth Table For SRAM Operations
HSB must remain HIGH for SRAM operations. Table 3. Truth Table for x8 Configuration CE H L L L WE X H H L OE X L H X High Z Data Out (DQ0-DQ7); High Z Data in (DQ0-DQ7); Inputs/Outputs[2] Read Output Disabled Write Mode Deselect/Power Down Standby Active Active Active Power
Table 4. Truth Table for x16 Configuration CE H L L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE[3] X H L H L L H L L H L BLE[3] X H L L H L L H L L H Inputs/Outputs[2] High-Z High-Z Data Out (DQ0-DQ15) Data Out (DQ0-DQ7); DQ8-DQ15 in High-Z Data Out (DQ8-DQ15); DQ0-DQ7 in High-Z High-Z High-Z High-Z Data In (DQ0-DQ15) Data In (DQ0-DQ7); DQ8-DQ15 in High-Z Data In (DQ8-DQ15); DQ0-DQ7 in High-Z Mode Deselect/Power Down Output Disabled Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Standby Active Active Active Active Active Active Active Active Active Active Power
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PRELIMINARY
CY14B101LA, CY14B101NA
Part Numbering Nomenclature
CY 14 B 101L A-ZS P 20 X C T Option: T - Tape and Reel Blank - Std.
Pb-Free
Temperature: C - Commercial (0 to 70C) I - Industrial (-40 to 85C)
P - 54 Pin Blank - 32/44/48 Die revision: Blank: No Rev A - 1st Rev
Package: ZS - 44 TSOP II SP - 48 SSOP SZ - 32 SOIC
Speed: 20 - 20 ns 25 - 25 ns 45 - 45 ns
Data Bus: L - x8 N - x16 Density: 101 - 1 Mb
Voltage: B - 3.0V NVSRAM 14 - AutoStore + Software STORE + Hardware STORE
Cypress
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PRELIMINARY
CY14B101LA, CY14B101NA
Ordering Information
Speed (ns) 20 Ordering Code CY14B101LA-ZS20XCT CY14B101LA-ZS20XC CY14B101LA-SP20XCT CY14B101LA-SP20XC CY14B101LA-SZ20XCT CY14B101LA-SZ20XC CY14B101NA-ZS20XCT CY14B101NA-ZS20XC CY14B101NA-ZSP20XCT CY14B101NA-ZSP20XC CY14B101LA-ZS20XIT CY14B101LA-ZS20XI CY14B101LA-SP20XIT CY14B101LA-SP20XI CY14B101LA-SZ20XIT CY14B101LA-SZ20XI CY14B101NA-ZS20XIT CY14B101NA-ZS20XI CY14B101NA-ZSP20XIT CY14B101NA-ZSP20XI 25 CY14B101LA-ZS25XCT CY14B101LA-ZS25XC CY14B101LA-SP25XCT CY14B101LA-SP25XC CY14B101LA-SZ25XCT CY14B101LA-SZ25XC CY14B101NA-ZS25XCT CY14B101NA-ZS25XC CY14B101NA-ZSP25XCT CY14B101NA-ZSP25XC CY14B101LA-ZS25XIT CY14B101LA-ZS25XI CY14B101LA-SP25XIT CY14B101LA-SP25XI CY14B101LA-SZ25XIT CY14B101LA-SZ25XI CY14B101NA-ZS25XIT CY14B101NA-ZS25XI CY14B101NA-ZSP25XIT CY14B101NA-ZSP25XI Package Diagram 51-85087 51-85087 51-85061 51-85061 51-85127 51-85127 51-85087 51-85087 51-85160 51-85160 51-85087 51-85087 51-85061 51-85061 51-85127 51-85127 51-85087 51-85087 51-85160 51-85160 51-85087 51-85087 51-85061 51-85061 51-85127 51-85127 51-85087 51-85087 51-85160 51-85160 51-85087 51-85087 51-85061 51-85061 51-85127 51-85127 51-85087 51-85087 51-85160 51-85160 Package Type 44-pin TSOP II 44-pin TSOP II 48-pin SSOP 48-pin SSOP 32-pin SOIC 32-pin SOIC 44-pin TSOP II 44-pin TSOP II 54-pin TSOP II 54-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-pin SSOP 48-pin SSOP 32-pin SOIC 32-pin SOIC 44-pin TSOP II 44-pin TSOP II 54-pin TSOP II 54-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-pin SSOP 48-pin SSOP 32-pin SOIC 32-pin SOIC 44-pin TSOP II 44-pin TSOP II 54-pin TSOP II 54-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-pin SSOP 48-pin SSOP 32-pin SOIC 32-pin SOIC 44-pin TSOP II 44-pin TSOP II 54-pin TSOP II 54-pin TSOP II Industrial Commercial Industrial Operating Range Commercial
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PRELIMINARY
CY14B101LA, CY14B101NA
Ordering Information (continued)
Speed (ns) 45 Ordering Code CY14B101LA-ZS45XCT CY14B101LA-ZS45XC CY14B101LA-SP45XCT CY14B101LA-SP45XC CY14B101LA-SZ45XCT CY14B101LA-SZ45XC CY14B101NA-ZS45XCT CY14B101NA-ZS45XC CY14B101NA-ZSP45XCT CY14B101NA-ZSP45XC CY14B101LA-ZS45XIT CY14B101LA-ZS45XI CY14B101LA-SP45XIT CY14B101LA-SP45XI CY14B101LA-SZ45XIT CY14B101LA-SZ45XI CY14B101NA-ZS45XIT CY14B101NA-ZS45XI CY14B101NA-ZSP45XIT CY14B101NA-ZSP45XI Package Diagram 51-85087 51-85087 51-85061 51-85061 51-85127 51-85127 51-85087 51-85087 51-85160 51-85160 51-85087 51-85087 51-85061 51-85061 51-85127 51-85127 51-85087 51-85087 51-85160 51-85160 Package Type 44-pin TSOP II 44-pin TSOP II 48-pin SSOP 48-pin SSOP 32-pin SOIC 32-pin SOIC 44-pin TSOP II 44-pin TSOP II 54-pin TSOP II 54-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-pin SSOP 48-pin SSOP 32-pin SOIC 32-pin SOIC 44-pin TSOP II 44-pin TSOP II 54-pin TSOP II 54-pin TSOP II Industrial Operating Range Commercial
All parts are Pb-free. This table contains Preliminary information. Contact your local Cypress sales representative for availability of these parts.
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PRELIMINARY
CY14B101LA, CY14B101NA
Package Diagrams
Figure 16. 44-Pin TSOP II (51-85087)
DIMENSION IN MM (INCH) MAX MIN.
22 1
PIN 1 I.D.
11.938 (0.470) 11.735 (0.462)
10.262 (0.404) 10.058 (0.396)
OR E KXA SG
23
44
EJECTOR PIN
TOP VIEW
BOTTOM VIEW
0.800 BSC (0.0315)
0.400(0.016) 0.300 (0.012)
BASE PLANE 0-5 0.10 (.004)
10.262 (0.404) 10.058 (0.396) 0.210 (0.0083) 0.120 (0.0047)
18.517 (0.729) 18.313 (0.721) 0.150 (0.0059) 0.050 (0.0020) 1.194 (0.047) 0.991 (0.039) SEATING PLANE
0.597 (0.0235) 0.406 (0.0160)
51-85087-*A
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PRELIMINARY
CY14B101LA, CY14B101NA
Package Diagrams
(continued) Figure 17. 48-Pin SSOP (51-85061)
51-85061 *C
Figure 18. 32-Pin SOIC (51-85127)
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PRELIMINARY
CY14B101LA, CY14B101NA
Package Diagrams
(continued) Figure 19. 54-Pin TSOP II (51-85160)
51-85160-**
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PRELIMINARY
CY14B101LA, CY14B101NA
Document History Page
Document Title: CY14B101LA, CY14B101NA 1 Mbit (128K x 8/64K x 16) nvSRAM Document Number: 001-42879 Orig. of Rev. ECN No. Submission Description of Change Date Change ** 2050747 See ECN UNC/PYRS New Data Sheet *A 2607447 11/14/2008 GVCH/AESA Removed 15 ns access speed Updated "Features" Updated Logic block diagram Added footnote 1 2, 3 and 7 Pin definition: Updated WE, HSB and NC pin description Page 4: Updated SRAM READ, SRAM WRITE, Autostore operation description Updated Figure 4 Page 4: Updated Hardware store operation and Hardware RECALL (Power up)description Page 4: Updated Software store and software recall description Footnote 1 and 11 referenced for Mode selection Table Added footnote 11 Updated footnote 9 and 10 Page 6: updated Data protection description Maximum Ratings:Added Max. Accumulated storage time Changed Output short circuit current parameter name to DC output current Changed ICC2 from 6mA to 10mA Changed ICC3 from 15mA to 35mA Changed ICC4 from 6mA to 5mA Changed ISB from 3mA to 5mA Added IIX for HSB Updated ICC1, ICC3, ISB and IOZ Test conditions Changed VCAP voltage min value from 68uF to 61uF Added VCAP voltage max value to 180uF Updated footnote 12 and 13 Added footnote 14 Added Data retention and Endurance Table Added thermal resistance value to 48-pin FBGA and 44-pin TSOP II packages Updated Input Rise and Fall time in AC test Conditions Referenced footnote 17 to tOHA parameter Updated All switching waveforms Updated footnote 17 Added footnote 20 Added Figure 10 (SRAM WRITE CYCLE:BHE and BLE controlled) Changed tSTORE max value from 12.5ms to 8ms Updated tDELAY value Added VHDIS, tHHHD and tLZHSB parameters Updated footnote 24 Added footnote 26 and 27 Software controlled STORE/RECALL Table: Changed tAS to tSA Changed tGHAX to tHA Changed tHA value from 1ns to 0 ns Added Figure 13 Added tDHSB parameter Changed tHLHX to tPHSB Updated tSS from 70us to 100us Added truth table for SRAM operations Updated ordering information and part numbering nomenclature *B 2654484 02/05/09 GVCH/PYRS Changed the data sheet from Advance information to Preliminary Referenced Note 15 to parameters tLZCE, tHZCE, tLZOE, tHZOE, tLZWE and tHZWE Updated Figure 12
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PRELIMINARY
CY14B101LA, CY14B101NA
Document Title: CY14B101LA, CY14B101NA 1 Mbit (128K x 8/64K x 16) nvSRAM Document Number: 001-42879 Orig. of Rev. ECN No. Submission Description of Change Date Change *C 2733909 07/09/09 GVCH/AESA Removed 48-ball FBGA package and added 54-pin TSOP II Package Corrected typo error in pin diagram of 48-pin SSOP Page 4; Added note to AutoStore Operation description Page 4; Updated Hardware STORE (HSB) Operation description Page 5; Updated Software STORE Operation description Added best practices Updated VHDIS parameter description Updated tDELAY parameter description Updated footnote 24 and added footnote 29
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at www.cypress.com/sales.
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(c) Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-42879 Rev. *C
Revised July 09, 2009
Page 24 of 24
All products and company names mentioned in this document are the trademarks of their respective holders.
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